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iso 7816 compatible xicor, inc. 1999 patents pending 9900-5004.4 2/12/99 ep 1 characteristics subject to change without notice 4k X76F400 512 x 8 bit functional diagram secure serialflash features 64-bit password security one array (496 bytes) two passwords (16 bytes) read password write password programmable passwords retry counter register allows 8 tries before clearing of the array 32-bit response to reset (rst input) 8 byte sector write mode 1mhz clock rate 2 wire serial interface low power cmos 2.0 to 5.5v operation standby current less than 1? active current less than 3 ma high reliability endurance: 100,000 write cycles data retention: 100 years available in: 8 lead pdip, soic,tssop and smart card module description the X76F400 is a password access security supervisor, containing one 3968-bit secure serialflash array. access to the memory array can be controlled by two 64-bit passwords. these passwords protect read and write operations of the memory array. the X76F400 features a serial interface and software protocol allowing operation on a popular two wire bus. the bus signals are a clock input (scl) and a bidirectional data input and output (sda). the X76F400 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards. the X76F400 utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. logic cs scl sda rst interface 8k byte data transfer array access enable reset response register password array and password verification logic chip enable retry counter serialflash array 32 byte serialflash array array 0 array 1 (password protected) (password protected) 7025 fm 01 logic scl sda rst interface 496 byte data transfer array access enable iso reset response register password array and password verification logic retry counter erase logic eeprom array
X76F400 2 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is an open drain serial data input/output pin. during a read cycle, data is shifted out on this pin. during a write cycle, data is shifted in on this pin. in all other cases, this pin is in a high impedance state. reset (rst) rst is a device reset pin. when rst is pulsed high the X76F400 will output 32 bits of ?ed data which conforms to the standard for ?ynchronous response to reset? the part must not be in a write cycle for the response to reset to occur. see figure 7. if there is power interrupted during the response to reset, the response to reset will be aborted and the part will return to the standby state. the response to reset is "mask programmable" only! device operation the X76F400 memory array consists of sixty-two 8-byte sectors. read or write access to the array always begins at the ?st address of the sector. read operations then can continue inde?itely. write operations must total 8 bytes. there are two primary modes of operation for the X76F400; protected read and protected write. protected operations must be performed with one of two 8-byte passwords. the basic method of communication for the device is generating a start condition, then transmitting a command, followed by the correct password. all parts will be shipped from the factory with all passwords equal to ?? the user must perform ack polling to determine the validity of the password, before starting a data transfer (see acknowledge polling.) only after the correct password is accepted and a ack polling has been performed, can the data transfer occur. to ensure the correct communication, rst must remain low under all conditions except when running a ?esponse to reset sequence? data is transferred in 8-bit segments, with each transfer being followed by an ack, generated by the receiving device. if the X76F400 is in a nonvolatile write cycle a ?o ack (sda=high) response will be issued in response to loading of the command byte. if a stop is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. the basic sequence is illustrated in figure 1. pin names pin configuration after each transaction is completed, the X76F400 will reset and enter into a standby mode. this will also be the response if an unsuccessful attempt is made to access a protected array. symbol description sda serial data input/output scl serial clock input rst reset input vcc supply voltage vss ground nc no connect sda v cc rst scl nc 1 2 3 4 7 8 6 5 soic v cc rst scl v ss nc sda smart card module nc nc nc gnd nc rst scl sda vss 1 2 3 4 7 8 6 5 pdip v cc nc nc nc v ss rst sda nc nc 1 2 3 4 7 8 6 5 v cc scl nc tssop
X76F400 3 figure 1. X76F400 device operation retry counter the X76F400 contains a retry counter. the retry counter allows 8 accesses with an invalid password before any action is taken. the counter will increment with any combination of incorrect passwords. if the retry counter over?ws, the memory area and both of the passwords are cleared to "0". if a correct password is received prior to retry counter over?w, the retry counter is reset and access is granted. device protocol the X76F400 supports a bidirectional bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter and the receiving device as a receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the X76F400 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda changes during scl high are reserved for indicating start and stop conditions. refer to figure 2 and figure 3. start condition all commands are preceeded by the start condition, which is a high to low transition of sda when scl is high. the X76F400 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. a start may be issued to terminate the input of a control byte or the input data to be written. this will reset the device and leave it ready to begin a new read or write command. because of the push/pull output, a start cannot be generated while the part is outputting data. starts are inhibited while a write is in progress. stop condition all communications must be terminated by a stop condition. the stop condition is a low to high transition of sda when scl is high. the stop condition is also used to reset the device during a command or data input sequence and will leave the device in the standby power mode. as with starts, stops are inhibited when outputting data and while a write is in progress. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. the X76F400 will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write condition have been selected, the X76F400 will respond with an acknowledge after the receipt of each subsequent eight-bit word. load command/address byte load 8-byte password verify password acceptance by use of ack polling read/write data bytes
X76F400 4 figure 2. data validity figure 3. definition of start and stop conditions table 1. X76F400 instruction set illegal command codes will be disregarded. the part will respond with a ?o-ack to the illegal byte and then return to the standby mode. all write/read operations require a password. command after start command description password used 1 s 5 s 4 s 3 s 2 s 1 s 0 0 sector write write 1 s 5 s 4 s 3 s 2 s 1 s 0 1 sector read read 1 1 1 1 1 1 0 0 change write password write 1 1 1 1 1 1 1 0 change read password write 0 1 0 1 0 1 0 1 password ack command none scl sda data stable data change scl sda start condition stop condition program operations sector write the sector write mode requires issuing the 8-bit write command followed by the password and then the data bytes transferred as illustrated in ?ure 4. the write command byte contains the address of the sector to be written. data is written starting at the ?st address of a sector and eight bytes must be transferred. after the last byte to be transferred is acknowledged a stop condition is issued which starts the nonvolatile write cycle. if more or less than 8 bytes are transferred, the data in the sector remains unchanged. ack polling once a stop condition is issued to indicate the end of the hosts write sequence, the X76F400 initiates the internal nonvolatile write cycle. in order to take advantage of the typical 5ms write cycle, ack polling can begin immediately. this involves issuing the start condition
X76F400 5 followed by the new command code of 8 bits (1st byte of the protocol.) if the X76F400 is still busy with the nonvolatile write operation, it will issue a ?o-ack in response. if the nonvolatile write operation has completed, an ?ck will be returned and the host can then proceed with the rest of the protocol. after the password sequence, there is always a nonvolatile write cycle. this is done to discourage random guesses of the password if the device is being tampered with. in order to continue the transaction, the X76F400 requires the master to perform a password ack polling sequence with the speci? command code of 55h. as with regular acknowledge polling the user can either time out for 10ms, and then issue the ack polling once, or continuously loop as described in the ?w. if the password that was inserted was correct, then an ?ck will be returned once the nonvolatile cycle in response to the passwrod ack polling sequence is over. if the password that was inserted was incorrect, then a ?o ack will be returned even if the nonvolatile cycle is over. therefore, the user cannot be certain that the pass- word is incorrect until the 10ms write cycle time has elapsed. read operations read operations are initiated in the same manner as write operations but with a different command code. sector read with sector read, a sector address is supplied with the read command. once the password has been acknowledged data may be read from the sector. an acknowledge must follow each 8-bit data transfer. a read operation always begins at the ?st byte in the sector, but may stop at any time. random accesses to the array are not possible. continuous reading from the array will return data from successive sectors. after reading the last sector in the array, the address is automatically set to the ?st sector in the array and data can continue to be read out. after the last bit has been read, a stop condition is generated without sending a preceding acknowledge. data ack polling sequence ack returned ? issue new command code write sequence completed enter ack polling issue start no yes proceed password ack polling sequence ack returned ? issue password ack command password load completed enter ack polling issue start no yes proceed
X76F400 6 figure 4. sector write sequence (password required) figure 5. acknowledge polling figure 6. sector read sequence (password required) ack p start write ack ack ack ack write password 7 write password 0 ack s sda . . . wait t wc or ack password command start password ack ack s command no-ack if ack, then password matches command stop host commands host commands X76F400 responce X76F400 response ack ack ack wait t wc data ack polling 8th clk. of 8th pwd. byte ?ck clk 8th clk ?ck clk ?ck start condition 8th bit ack or no ack scl sda data n ack p start read ack ack ack ack read password 7 read password 0 ack data 0 s sda . . . wait t wc or ack password command start password ack ack s command no-ack if ack, then password matches command stop host commands host commands X76F400 responce X76F400 response
X76F400 7 passwords passwords are changed by sending the "change read password" or "change write password" commands in a normal sector write operation. a full eight bytes containing the new password must be sent, following successful transmission of the current write password and a valid password ack response. the user can use a repeated ack polling command to check that a new password has been written correctly. an ack indicates that the new password is valid. there is no way to read any of the passwords. response to reset (default = 19 40 aa 55) the iso response to reset is controlled by the rst and clk pins. when rst is pulsed high during a clock pulse, the device will output 32 bits of data, one bit per clock, and it resets to the standy state. this conforms to the iso standard for ?ynchronous response to reset? the part must not be in a write cycle for the response to reset to occur. after initiating a nonvolatile write cycle the rst pin must not be pulsed until the nonvolatile write cycle is complete. if not, the iso response will not be activated. if the rst is pulsed high and the clk is within the rst pulse (meet the t nol spec.) in the middle of an iso transaction, it will output the 32 bit sequence again (starting at bit 0). otherwise, this aborts the iso operation and the part returns to standby state. if the rst is pulsed high and the clk is outside the rst pulse (in the middle of an iso transaction), this aborts the iso operation and the part returns to standby state. if there is power interrupted during the response to reset, the response to reset will be aborted and the part will return to the standby state. a response to reset is not available during a nonvolatile write cycle. figure 7. response to reset (rst) sck so rst byte 0 msb lsb lsb msb 1 lsb msb lsb msb 2 3 1 0 0 0 0 11 1 0 0 1 0 0 0 0 0 00 0 0 1 1 0 1 1 1 0 0 0 1 1 0 absolute maximum ratings* temperature under bias ..................... ?5? to +135? storage temperature ..........................?5? to +150? voltage on any pin with respect to v ss .......................................?v to +7v d.c. output current.................................................. 5ma lead temperature (soldering, 10 seconds).................................. 300? *comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
X76F400 8 recommended operating conditions temp min. max. commercial 0? +70? industrial ?0? +85? supply voltage limits X76F400 4.5v to 5.5v X76F400 ?2 2.0v to 5.5v d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) capacitance t a = +25?, f = 1mhz, v cc = 5v notes: (1) must perform a stop command after a read command prior to measurement (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 1ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = v ss i cc2 (3) v cc supply current (write) 3ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = v ss i sb1 (1) v cc supply current (standby) 1a v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400 khz, f sda = 400 khz i sb2 (1) v cc supply current (standby) 1a v sda = v scc = v cc other = gnd or v cc ?.3v i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v il (2) input low voltage ?.5 v cc x 0.1 v v ih (2) input high voltage v cc x 0.9 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma symbol test max. units conditions c out (3) output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (rst, scl) 6 pf v in = 0v equivalent a.c. load circuit a.c. test conditions 3v 1.3k w output 100pf 5v 1.53k w output 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf
X76F400 9 ac characteristics (t a = -40?c to +85?c, v cc = +2.0v to +5.5v, unless otherwise speci?d.) notes: 1. c b = total capacitance of one bus line in pf 2. t aa = 1.1? max below v cc = 2.0v. reset ac specifications power up timing notes: 1. delays are measured from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. 2. typical values are for t a = 25?c and v cc = 5.0v nonvolatile write cycle timing notes: 1. t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. symbol parameter min max units f scl scl clock frequency 0 1 mhz t aa (2) scl low to sda data out valid 0.1 0.9 m s t buf time the bus must be free before a new transmission can start 1.2 m s t hd:sta start condition hold time 0.6 m s t low clock low period 1.2 m s t high clock high period 0.6 m s t su:sta start condition setup time (for a repeated start condition) 0.6 m s t hd:dat data in hold time 10 ns t su:dat data in setup time 100 ns t r sda and scl rise time 20+0.1xc b (1) 300 ns t f sda and scl fall time 20+0.1xc b (1) 300 ns t su:sto stop condition setup time 0.6 m s t dh data out hold time 0 m s t nol rst to scl non-overlap 500 ns t rdv rst low to sda valid during response to reset 0 450 ns t cdv clk low to sda valid during response to reset 0 450 ns t rst rst high time 1.5 m s t su:rst rst setup time 500 ns symbol parameter min. typ (2) max. units t pur (1) time from power up to read 1 ms t puw (1) time from power up to write 5 ms symbol parameter min. typ.(1) max. units t wc (1) write cycle time 5 10 ms
X76F400 10 bus timing write cycle timing rst timing diagram ?response to a synchronous reset t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high scl sda t wc 8th bit of last byte ack stop condition start condition t rst t nol t high_rst t low_rst t cdv t rdv t su:rst data bit (1) data bit (2) 1st clk pulse 2nd clk pulse 3rd clk pulse i/o clk rst t nol
X76F400 11 guidelines for calculating typical values of bus pull up resistors 100 80 60 40 20 bus capacitance in pf pull up resistance in k w r min r max 20 40 60 80 100 r min v ccmax i olmin -------------------------- 1 . 8 k w == r max t r c bus ----------------- - = t r = maximum allowable sda rise time
X76F400 12 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ . 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
X76F400 13 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
X76F400 14 note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (7.72) all measurements are typical (4.16) (1.78) (0.42)
X76F400 15 note: all measurements in millimeters 8 contact module 11.4 12.6 1.59 0.15 1.215 1.62 1.62 2.54 2.54 90 6 contact module 8 1.3 1.3 0.2 0.2 10.62 1.31 1.31 reject punch position 1.422 1.422 14.25 35 23.02 8.82 4.75 1 35mm tape 35mm tape
X76F400 16 ordering information v cc limits blank = 5v ?0% 2.0 = 2.0v to 5.5v temperature range blank = commercial = 0? to +70? i = industrial= ?0? to +85? package s8 = 8-lead soic p = 8-lead pdip v8 = 8-lead tssop h = die in waffle packs w = die in wafer form x = smart card module y = smart card device X76F400 x x ? part mark convention 8-lead tssop eyww xxx 8-lead soic/pdip X76F400 x xx blank = 8-lead soic d = 2.0 to 5.5v, 0 to +70? e = 2.0 to 5.5v, -40 to +85? blank = 4.5 to 5.5v, 0 to +70? i = 4.5 to 5.5v, -40 to +85? limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,88 3, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expe cted to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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